The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device and a core voltage generating method for stabilization of the core voltage during a refresh operation of the semiconductor memory device.
Generally, a semiconductor memory device is supplied with an external voltage VDD, and lowers a voltage level of the external voltage VDD to voltage levels of a core voltage VCORE and a peri voltage VPERI for operation of the semiconductor memory device; herein, the core voltage VCORE is used for reading data from a memory cell or writing data to the memory cell, and the peri voltage VPERI is used for operating internal circuits included in the semiconductor memory device.
Typically, in a conventional semiconductor memory device, a voltage level of the core voltage VCORE becomes unstable because excessive power consumption is occurred when a bit line is charged.
A core voltage generator raises the unstable core voltage VCORE to a stable voltage level. The core voltage generator determines whether or not the core voltage VCORE is stable by comparing the core voltage VCORE with a reference voltage VRC.
Herein, when the core voltage VCORE is unstable, an over driving controller is activated to drive the external voltage VDD over the core voltage VCORE.
RTOE and SBE are signals for the bit line charging. The conventional semiconductor memory device slows down activating speed of the RTOE and SBE to slow down power consuming speed of the core voltage VCORE during the bit line charging.
That is, the RTOE and SBE are activated to a logic xe2x80x98LOWxe2x80x99 level and to a logic xe2x80x98HIGHxe2x80x99 level respectively, and a predetermined time is needed to change levels of the RTOE and SBE. The semiconductor memory device extends the predetermined time so that the RTOE and SBE are activated slowly. Therefore, a voltage level of the core voltage VCORE is slowly downed.
FIG. 1 is a block diagram showing a power supply unit included in the conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes an over driving controller 11, a core voltage generator 10, a bit line sensing amplifier 12 and a bit line sensing amplifier controller 13.
The over driving controller 11 receives a bit line sensing start signal SEST30 and generates an over driving control signal SENSE_EN for driving an external voltage VDD over a core voltage VCORE. The core voltage generator 10 generates the core voltage VCORE for operating the bit line sensing amplifier 12 in response to the bit line sensing start signal SEST30 and the over driving control signal SENSE_EN.
The bit line sensing amplifier 12 amplifies a potential difference between a bit line pair BL and BLB. The bit line sensing amplifier controller 13 generates a first enable signal RTOE and a second enable signal SBE. Herein, the first enable signal RTOE and the second enable signal SBE are for enabling a first activating voltage RTO (not shown) and a second activating voltage SB (not shown) each, where the first activating voltage RTO and the second activating voltage SB are for operating the bit line sensing amplifier 12.
FIG. 2 is a circuit diagram showing the core voltage generator 10 shown in FIG. 1.
As shown, the core voltage generator 10 includes a control unit 101, a comparing unit 102, a core voltage comparing operator 103 and an over driving unit 104.
The control unit 101 turns on or off the comparing unit 102 depending on the bit line sensing start signal SEST30. The comparing unit 102 compares the reference voltage VRC with the core voltage VCORE to generate an enable signal COMP_EN depending on the comparison result. The over driving unit 104 generates the core voltage VCORE in response to the over driving control signal SENSE_EN.
The control unit 101 has an inverter I3, a PMOS transistor P1 and NMOS transistors N4 and N5.
Herein, the inverter I3 inverts the bit line sensing start signal SEST30. An output of the inverter I3 is connected to a gate of the PMOS transistor P1 and a source of the P1 is connected to an external voltage VDD. A gate of the NMOS transistor N4 is connected to the output of the inverter I3, a drain of the N4 is connected to a drain of the P1, a source of the N4 is connected to a ground voltage VSS. A drain and a gate of the NMOS transistor N5 are connected to the drain of the P1, a source of the N5 is connected to the ground voltage VSS.
The comparing unit 102 has PMOS transistors P2, P3, P4 and P5; and also has NMOS transistors N1, N2, N3, N6, N7, N8 and N9.
Herein, the P2 is paired with the P3 constituting a differential amplifying unit, and the P4 is paired with the P5 also constituting the differential amplifying unit. The N2 is controlled by the reference voltage VRC, and the N3 is controlled by the core voltage VCORE. The N2 and N3 are input units for the differential amplifying unit. The N7 severs as a current source for the differential amplifying unit. A gate of the N1 is connected to the reference voltage VRC and a source of the N1 is connected to a power voltage VDD. A gate of the N6 is connected to the gate of the N5. The N6 is connected between the drain of the N1 and the ground voltage VSS. A gate of the N8 is connected to the gate of the N7, and connected between the drain of the N9 and the ground voltage VSS.
Herein, the gate of the N3 is connected to the drain of the N9, and the gate of the N2 is connected to the drain of the N1.
A gate of the P6 included in the core voltage comparing operator 103 receives an enable signal COMP_EN. A source of the P6 is connected to the power voltage VDD and a drain of the P6 is connected to a gate of the N9.
A gate of the P7 included in the over driving unit 104 receives the sense enable signal SENSE_EN. A source of the P7 is connected to the power voltage VDD and a drain of the P7 is connected to the gate of the N9.
FIGS. 3A and 3B are circuit diagrams showing two different embodiments of the over driving controller 11. A first embodiment shown in FIG. 3A is provided with a plurality of inverters. Meanwhile, a second embodiment shown in FIG. 3B is provided with a plurality of PMOS capacitors.
As described above, the over driving controller 11 generates the over driving control signal SENSE_EN for driving the power voltage VDD over the core voltage VCORE after the conventional semiconductor memory device is activated.
Referring to FIG. 3A, the over driving controller 11 includes inverters I31 to I37 and a NAND gate NAND31.
The inverters I31 to I37 invert and delay a bit line sensing start signal SEST30. The NAND gate NAND31 receives the bit line sensing start signal SEST30 and an outputted signal from the inverters I31 to I37, and performs NAND operation on the two received signals, i.e., the bit line sensing start signal SEST30 and the outputted signal from the inverters I31 to I37.
Referring to FIG. 3B, the over driving controller 11 further includes inverters I38 to I43, a NAND gate NAND32, an NMOS transistor N31 and PMOS transistors P31 to P38.
FIGS. 4A and 4B are circuit diagrams showing the bit line sensing amplifier 12.
FIG. 4A shows a power supplying unit of the bit line sensing amplifier 12, and FIG. 4B shows an amplifying unit of the bit line sensing amplifier 12.
Referring to FIG. 4A, the power supplying unit of the bit line sensing amplifier 12 includes a first supplying unit 40 and a second supplying unit 41.
Herein, a first activating voltage RTO is supplied power by the core voltage VCORE or the power voltage VDD in response to first enable signal RTOE. A second activating voltage SB is supplied power by the ground voltage VSS in response to a second enable signal SBE.
The first supplying unit 40 is formed by a PMOS transistor P41; herein, a gate of the P41 is connected to the first enable signal RTOE, a source of the P41 is connected to the core voltage VCORE and outputs the first activating voltage RTO from a drain of the P41.
The second supplying unit 41 is formed by an NMOS transistor N41; herein, a gate of the N41 is connected to the second enable signal SBE, a source of the N41 is connected to the ground voltage VSS and outputs the second activating voltage SB from a drain of the N41.
Referring to FIG. 4B, the amplifying unit of the bit line sensing amplifier 12 includes cross-coupled four transistors N51, N52, P51 and P52.
FIG. 5 is a circuit diagram showing the bit line sensing amplifier controller 13 shown in FIG. 1.
As described above, the bit line sensing amplifier controller 13 receives the bit line sensing start signal SEST30 and the refresh signal REFB, and generates the first enable signal RTOE and the second enable signal SBE for enabling the first activating voltage RTO and the second activating voltage SB shown in FIGS. 4A and 4B.
As shown, the bit line sensing amplifier controller 13 is provided with inverters I51 to I54, PMOS transistors P51 to P54, NMOS transistors N51 to N54 and resistors R51 and R52.
The I51 and I52 are connected serially and delay the bit line sensing start signal SEST30 for a predetermined time. The delayed bit line sensing start signal SEST30 is inputted to a gate of the P51, and the P51 outputs the first enable signal RTOE through its drain.
A gate of the N51 is connected to the gate of the P51 and controlled by the bit line sensing start signal SEST30. Drains of the N52 and N53 are connected to a source of the N51 and their gates are connected to the power voltage VDD and the refresh signal REFB respectively.
The resistor R51 is serially connected to the N52 and the ground voltage. The I53 is for inverting the bit line sensing start signal SEST30.
The inverted bit line sensing start signal SEST30 is inputted to a gate of the P54 and controls the P54. The P54 outputs the second enable signal SBE from its drain. The N54 is controlled by the bit line sensing start signal SEST30 and its gate and source are connected to the gate of the P4 and the ground voltage VSS respectively.
One end of the resistor R52 is connected to the power voltage VDD, and the other end of the R52 is connected to the P52 and P53. The T54 inverts the refresh signal REFB. Gates of the P52 and P53 are connected to the power voltage VDD and the inverted refresh signal REFB respectively.
Referring to FIGS. 1 to 5, an operation of the power supply unit included in the conventional semiconductor memory device is described below.
If the power supply unit is activated, the bit line sensing start,signal SEST30 becomes a logic xe2x80x98HIGHxe2x80x99 level, and the core voltage generator 10, the over driving controller 11 and the bit line sensing amplifier are enabled or start to operate.
If the bit line sensing start signal SEST30 becomes a logic xe2x80x98HIGHxe2x80x99 level, the core voltage generator 10 enables the comparing unit 102 for comparing the reference voltage VRC with the core voltage VCORE.
Herein, if the core voltage VCORE becomes lower than the reference voltage VRC, the enable signal COMP_EN becomes a logic xe2x80x98LOWxe2x80x99 level and the PMOS transistor P6 is turned on driving the power voltage VDD over the core voltage VCORE. If the core voltage VCORE is higher than the reference voltage VRC, the COMP_EN becomes a logic xe2x80x98HIGHxe2x80x99 level and the PMOS transistor P6 is turned off separating the power voltage VDD from the core voltage VCORE.
The PMOS transistor P7 included in the over driving unit 104 controlled by the over driving control signal SENSE_EN to drive the power voltage VDD over the core voltage VCORE.
The over driving controller 11 generates the over driving control signal SENSE_EN if the bit line sensing start signal SEST30 becomes a logic xe2x80x98HIGHxe2x80x99 level. As described above, the over driving controller 11 can be embodied like a circuit shown in FIG. 3A or a circuit shown in FIG. 3B.
If the bit line sensing amplifier 12 is activated, the first enable signal RTOE generated from the bit line sensing amplifier 13 is enabled to turn on the PMOS transistor P41, and the first activating voltage RTO for operating the bit line sensing amplifier 12 is supplied with the core voltage VCORE.
At the same time, the second enable signal SBE is enabled to turn on the NMOS transistor N41, and the second activating voltage SB for operating the bit line sensing amplifier 12 is supplied power by the ground voltage VSS.
Therefore, the bit line sensing amplifier 12 consumes the first activating voltage RTO supplied with the core voltage VCORE for bit line charging. In the bit line sensing amplifier controller 13 shown in FIG. 5, if the bit line sensing start signal SEST30 becomes a logic xe2x80x98HIGHxe2x80x99 level, the first enable signal RTOE becomes a logic xe2x80x98LOWxe2x80x99 level and the second enable signal SBE becomes a logic xe2x80x98HIGHxe2x80x99 level.
Meanwhile, in the bit line sensing amplifier controller 13, the resistors R51 and R52 are included for controlling activating speed of the first enable signal RTOE and the second enable signal SBE so that the RTOE and the SBE can be activated slowly.
Therefore, the core voltage VCORE is merely lost during the refresh operation.
FIGS. 6 and 7 are timing diagrams showing variations of the core voltage VCORE during the normal operation shown in FIG. 6 and the refresh operation shown in FIG. 7 of the conventional semiconductor memory device.
As shown in FIG. 6, at the normal operation, the timing of driving the power voltage VDD over the core voltage VCORE is same as the timing of consuming the core voltage VCORE.
However, as shown in FIG. 7, at the refresh operation, the timing of driving the power voltage VDD over the core voltage VCORE is different from the timing of consuming the core voltage VCORE, whereby the core voltage VCORE rises excessively.
It is, therefore, an object of the present invention is to provide a semiconductor memory device for stabilizing a core voltage during a refresh operation.
In accordance with an aspect of the present invention, there is provided a core voltage control device including a bit line sensing start signal controller for receiving a bit line sensing start signal to generate a delayed bit line sensing start control signal in response to a refresh signal; a core overdriving controller for generating an overdriving control signal in response to the delayed bit line sensing start signal; and a core voltage generator for generating the core voltage in response to the delayed bit line sensing start signal and the overdriving control signal to thereby provide core voltage to the bit line sensing amplifier after a predetermined delayed time from the bit line sensing start control signal.